Sr Application Engineer - FAST Team Cadence Design Systems
Austin, TX

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

* As a member of the FasT SoC Development team, the individual is responsible for generating micro-architecture definitions, module-level implementation and verification, synthesis, timing analysis and post silicon validation support.
* This individual should be able to fully comprehend various ARM processor architectures, Fabrics and Interconnects, and various Bus protocols such as AXI, AHB and APB.
* Works with physical design engineers to specify timing constraints, perform timing analysis, and assist in final timing sign-off.

Required Skills

* BS with industry experience. MS is preferred.
* Minimum of 2-4 years of experience in SoC Design with emphasis on module implementation and verification
* Should be fluent in Verilog/System Verilog
* Knowledge of Digital Frontend Tools & Implementation: Simulation, Waveform debugging, Linting, Formal Logic Equivalence, logic synthesis, STA, and CDC checks
* Proven knowledge of logic synthesis, static timing analysis, and DFT is a plus
* Knowledge of low power implementation including UPF/CPF
* Strong problem-solving skills to quickly identify and provide solutions on projects with demanding schedules
* Excellent communication skills

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